1. Field of the Invention
The present invention relates to a capacitor having a tantalum lower electrode and a method of fabricating the same.
2. Background of the Related Art
Capacitors are found in numerous semiconductor devices. Despite the proliferation of various types of capacitors, large amounts of effort are still expended in attempts to obtain capacitors that have particular electrical characteristics and can also be easily fabricated using modem semiconductor fabrication technologies.
One specific capacitor of this type that has been proposed is a capacitor that uses tantalum to form its lower electrode. For example, U.S. Pat. No. 5,142,438 describes such a capacitor. This lower electrode, through buried contacts, electrically connects to the word and bit lines of a semiconductor DRAM memory. The tantalum layer is thereafter subjected to a rapid thermal processing or furnace heating which creates a tantalum silicide layer at the tantalum layer's interface with the silicon substrate, and an insulating tantalum pentoxide dielectric layer at the top of the tantalum layer. After depositing a layer of barrier material such as silicon nitride, a polysilicon electrode layer is deposited on the structure and doped.
While the above-described approach allows for the creation of a dielectric layer over a conducting layer without specifically applying a distinct dielectric layer, the applications in which this device can be used are limited due to a number of considerations.
For example, when the capacitor is used in a DRAM as disclosed in the '438 patent, its charge storage need not be very great. Accordingly, the very thin tantalum pentoxide layer that is formed can be used. Consequently, a correspondingly thin deposited tantalum layer can be used to form the tantalum pentoxide layer. If, however, a thicker tantalum pentoxide layer was needed in order to allow for greater charge storage, a thicker original tantalum layer would be used. This cannot, however, be easily achieved, since thick tantalum layers are known to exhibit stress characteristics that lead to warpage of the wafer on which it is formed.